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ADNS-2030 low power optical mouse sensor data sheet description the ADNS-2030 is a low-power optical mouse sensor used to implement a non-mechanical tracking engine for com - puter mice. with a 3.3 v power supply and power-saving sleep functions, this sensor is particularly suited to cord - less mouse applications. it is based on optical navigation technology, which mea - sures changes in position by optically acquiring sequen - tial surface images (frames) and mathematically deter - mining the direction and magnitude of movement. the sensor is housed in a 16-pin staggered dual inline pack - age (dip) that is designed for use with the hdns - 2100 lens and hdns - 2200 clip and hlmp-ed80-xx000 (639 nm led illuminator source). there are no moving parts, and precision optical alignment is not required, facilitating high volume assembly. the output format is two channel quadrature (x and y direc - tion) which emulates encoder photo-transistors. the current x and y information are also available in registers accessed via a serial port. default resolution is specifed as 400 counts per inch, with rates of motion up to 14 inches per second. resolu - tion can also be programmed to 800 cpi. the part is programmed via a two wire serial port, through registers. theory of operation the ADNS-2030 is based on optical navigation technol - ogy. it contains an image acquisition system (ias), a digi - tal signal processor (dsp) and a two channel quadrature output, and a two wire serial port. the ias acquires microscopic surface images via the lens and illumination system provided by the hdns-2100, hdns-2200 and hlmp-ed80-xx000. these images are processed by the dsp to determine the direction and dis - tance of motion. the dsp generates the ? x and ? y relative displacement values that are converted to two channel quadrature signals. features ? precise optical navigation technology ? no mechanical moving parts ? complete 2d motion sensor ? serial interface and/or quadrature interface ? smooth surface navigation ? programmable frame speed up to 2300 frames per sec (fps) ? accurate motion up to 14 ips ? 800 cpi resolution ? high reliability ? high speed motion detector ? wave solderable ? single 3.3 volt power supply ? shutdown pin for usb suspend mode operation ? power conservation mode during times of no move - ment ? on chip led drive with regulated current ? serial port registers C programming C data transfer ? 16-pin staggered dual inline package (dip) applications ? cordless optical mice ? mice for desktop pcs, workstations, and portable pcs ? trackballs ? integrated input devices
pinout of ADNS-2030 optical mouse sensor pin number pin description 1 sclk serial port clock (input) 2 xa xa quadrature output 3 xb xb quadrature output 4 yb yb quadrature output 5 ya ya quadrature output 6 xy_led led control 7 refa internal reference 8 refb internal reference 9 osc_in oscillator input 10 gnd system ground 11 osc_out oscillator output 12 gnd system ground 13 v dd 3.3 volt power supply 14 r_bin led current bin resistor 15 pd power down pin, active high 16 sdio serial data (input and output) figure 2. package outline drawing of ADNS-2030 optical mouse sensor. figure 1. top view. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. 8 7 6 5 4 3 2 1 sclk xa xb yb ya xy_led re fa refb gnd osc_in osc_o u t gnd v dd sdio pd r_bi n 9 10 16 15 14 13 12 11 a2030 xyywwz notes: 1. dimensions in mm/in. 2. dimensonal tolerance: 0.1 mm 3. coplanarity of leads: 0.1 mm 4. lead pitch tolerance: 0.15 mm 5. cumula tive pitch tolerance: 0.15 mm 6. angular tolerance: 3.0 7. maximum flash +0.2 mm 8. chamfer (25 x 2) on the ta per side of the lead. 0.25 0.010 5 typ kapt0n ta pe lead widt h lead offset lead pitc h 1.42 0.056 3.18 0.125 0.99 0.039 5.15 0.203 6.17 0.243 2.54 0.100 1.27 0.050 0.50 0.020 13.38 0.527 4.55 0.179 6.02 0.237 12.34 0.486 9.10 0.358 22.30 0.878 5.60 0.220 0.80 0.032 a2030 xyywwz pin 1
3 . 5 0 0 . 1 3 8 0 r e f 0 r e f c l e a r z o n e 0 . 0 9 1 2 . 3 2 1 . 1 9 4 3 0 . 3 2 1 . 5 5 1 3 9 . 3 9 1 . 5 9 6 4 0 . 5 3 0 . 0 5 0 1 . 2 7 0 . 4 4 8 1 1 . 3 8 0 . 4 9 6 1 2 . 6 0 0 . 2 9 5 7 . 5 0 0 . 2 0 1 5 . 1 0 0 . 0 4 8 1 . 2 2 0 . 0 5 0 1 . 2 8 0 . 5 4 6 1 3 . 8 8 a l l d i m e n s i o n s i n c h m m 0 . 8 0 . 0 3 1 r e c o m m e n d e d ( 1 6 p l a c e s ) b a s e p l a t e p l a s t i c s p r i n g c l i p b a s e p l a t e a l i g n m e n t p o s t s e n s o r p c b e s d l e n s r i n g 7 . 4 5 0 . 2 9 3 4 4 . 2 9 1 . 7 4 4 1 9 . 1 0 0 . 7 5 2 1 3 . 8 2 0 . 5 4 4 1 0 . 5 8 0 . 4 1 7 1 4 . 5 8 0 . 5 7 4 d i m e n s i o n s i n m m / i n . + x + y ( t o p v i e w ) ( s i d e v i e w ) overview of optical mouse sensor assembly 2d assembly drawing of ADNS-2030 figures 3 and 4, shown with hdns- 2100, hdns-2200 and hlmp-ed80- xx000. avago technologies provides an iges fle drawing describing the base plate molding features for lens and pcb alignment these components interlock as they are mounted onto defned features on the base plate. the ADNS-2030 sensor is designed for mounting on a through hole pcb, looking down. there is an aperture stop and features on the package that align to the lens. the hdns-2100 lens provides optics for the imaging of the surface as well as illumination of the surface at the optimum angle. features on the lens align it to the sensor, base plate, and clip with the led. the lens also has a large round fange to provide a long creepage path for any esd events that occur at the opening of the base plate. the hdns-2200 clip holds the led in relation to the lens. the led must be inserted into the clip and the leds leads formed prior to loading on the pcb. the clip interlocks the sensor to the lens, and through the lens to the alignment features on the base plate. the hlmp-ed80-xx000 led is recom - mended for illumination. if used with the bin table, sufcient illumination can be guaranteed. figure 5. exploded view drawing. figure 3. recommended pcb mechanical cutouts and spacing (top view). figure 4. 2d assembly drawing of ADNS-2030 (top and side view). h d n s - 2 2 0 0 ( c l i p ) h l m p - e d 8 0 - x x 0 0 0 ( l e d ) a d n s - 2 0 3 0 ( s e n s o r ) c u s t o m e r s u p p l i e d p c b h d n s - 2 1 0 0 ( l e n s ) c u s t o m e r s u p p l i e d b a s e p l a t e w i t h r e c o m m e n d e d a l i g n m e n t f e a t u r e s p e r i g e s d r a w i n g
pcb assembly considerations 1. insert the sensor and all other electrical components into pcb. 2. bend the led leads 90 and then insert the led into the assembly clip until the snap feature locks the led base. 3. insert the led/clip assembly into pcb. 4. wave solder the entire assembly in a no-wash solder process utilizing solder fixture. the solder fixture is needed to protect the sensor during the solder process. the fxture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. the solder fxture is also used to set the reference height of the sensor to the pcb top during wave soldering (note: do not remove the kapton tape during wave soldering). 5. place the lens onto the base plate. 6. remove the protective kapton tape from optical aperture of the sensor. care must be taken to keep contaminants from entering the aperture. it is recom - mended not to place the pcb facing up during the entire mouse assembly process. the pcb should be held vertically during the kapton removal process. 7. insert pcb assembly over the lens onto the base plate aligning post. the sensor aperture ring should self- align to the lens. figure 6. block diagram of ADNS-2030 optical mouse sensor. figure 7. pcb assembly. 8. the optical position reference for the pcb is set by the base plate and lens. note that the pcb motion due to button presses must be minimized to maintain optical alignment. 9. install mouse top case. there must be a feature in the top case to press down onto the clip to ensure all components are interlocked to the correct vertical height. design considerations for improving esd performance the fange on the lens has been designed to increase the creepage and clearance distance for electrostatic discharge. the table below shows typical values assum - ing base plate construction per the avago supplied iges fle and hdns-2100 lens fange. typical distance millimeters creepage 16.0 clearance 2.1 for improved esd performance, the lens fange can be sealed (i.e. glued) to the base plate. note that the lens material is polycarbonate and therefore, cyanoacrylate based adhesives or other adhesives that may damage the lens should not be used. q u a d r a t u r e o u t p u t i m a g e p r o c e s s o r p o w e r o n r e s e t p o w e r i n p u t s 3 . 3 v o l t p o w e r p d g n d r e f b l e d d r i v e o s c i l l a t o r l e d r e s o n a t o r o s c _ i n o s c _ o u t x y _ l e d x b x a r _ b i n q u a d r a t u r e o u t p u t s y a y b s e r i a l p o r t s c l k s d i o v d d g n d s e r i a l p o r t r e f a v o l t a g e r e f e r e n c e p c b s e n s o r l e d b a s e p l a t e l e n s / l i g h t p i p e c l i p s u r f a c e
figure 8. typical application for cordless optical mouse. v dd (3v) 0.1 f gnd v dd 13 gnd sclk sdio pd xa 2 3 4 5 r1 = 15k xb yb ya 15 1 16 10 12 p1.7 p1.6 8 9 7 20 19 xtal1 12 mhz xtal2 1 4 5 18 p3.4 p3.5 p3.0 p3.1 p3.2 p3.3 vcc rst 10 gnd xy_led 6 9 11 7 8 14 4.7 f surface 18 mhz 0.1 f 2.2 f ceramic resonator avx kbr-18-00-msa murata csa18.00mxz040 hdns 2100 lens internal image sensor hlmp-ed80-xx000 r_bin osc_in refb refa osc_out ADNS-2030 3.0 volt c lm3352 p1.5 17 14 r l m buttons 15 16 p1.2 p1.3 p1.4 40 pf 40 pf gnd shld 2 3 6 gnd qa qb v dd r z led v dd rf transmitter circuitry gnd c3 ? recommended typical application (transmitter side) c3+ c2 ? c2+ c1 ? c1+ vout gnd c fi l nsd v in gnd gnd gnd 16 14 12 9 15 13 10 15 f 0.33 f 3.3 v r2 = 2.7 11 1 2 3 4 5 6 7 8 nc 1 f 0.33 f 0.33 f 100 f 0.1 f v dd (5v) d+ d- gnd shld p0.7 p0.6 p0.5 12 8 1.3 k 13 7 11 16 15 xtalin 6 mhz (optional) xtalout 6 10 9 17 d- vreg rf receiver circuitry d+ vpp v dd vss cypress cy7c63723a-pc recommended typical application (receiver side) r1 value (ohms) 15 15 15 15 15 18 22 27 33 37 k l m n p q r s t u led bin
notes on bypass capacitors ? caps for pins 7, 8 and 12, 13 must have trace lengths less than 5 mm. ? the 0.1 f caps must be ceramic. ? caps should have less than 5 nh of self inductance. ? caps should have less than 0.2? of esr. ? surface mount parts are recommended. regulatory requirements ? passes fcc b and worldwide analogous emission limits when assembled into a mouse with unshielded cable and following avago recommendations. ? passes en61000-4-4/iec801-4 eft tests when as - sembled into a mouse with unshielded cable and following avago recommendations. ? ul fammability level ul94 v-0. ? provides sufcient esd creepage/clearance distance to avoid discharge up to 15kv when assembled into a mouse according to usage instructions above. ? for eye safety consideration, please refer to the docu - ment, eye safety calculation an1228 available on the web site, http://www.avago.com/view/opticalnaviga - tion. ? the 15.0 k? resistor is determined by the absolute maximum rating of 50 ma for the hlmp-ed80-xx000 . the other resistor values for brighter bins will guarantee sufcient intensity with reduced power. absolute maximum ratings parameter symbol minimum maximum units notes storage temperature t s -40 85 c operating temperature t a -15 55 c lead solder temp 260 c for 10 seconds, 1.6 mm below seating plane supply voltage v dd -0.5 3.6 v esd 2 kv all pins, human body model mil 883 method 3015 input voltage v in -0.5 v dd +0.5 v all i/o pins
recommended operating conditions parameter symbol minimum typical maximum units notes operating temperature t a 0 40 c power supply voltage v dd 3.0 3.3 3.6 volts power supply rise time v rt 100 ms supply noise v n 30 mv peak to peak @27 mhz bandwidth clock frequency f clk 17.4 18.0 18.7 mhz set by ceramic resonator serial port clock frequency sclk f clk /4 mhz resonator impedance x res 55 distance from lens reference z 2.3 2.4 2.5 mm results in 0.2 mm dof plane to surface (see figure 9.) speed s 0 14 in/sec @ frame rate = 1500 fps acceleration a 0.15 g @ frame rate = 1500 fps light level onto ic irr inc 80 25,000 mw/m 2 = 639 nm 100 30,000 = 875 nm sdio read hold time t hold 100 s hold time for valid data (refer to figure 27.) sdio serial write-write time t sww 100 s time between two write commands (refer to figure 30.) sdio serial write-read time t swr 100 s time between write and read operation (refer to figure 31.) sdio serial read-write time t srw 120 ns time between read and write operation (refer to figure 32.) sdio serial read-read time t srr 120 ns time between two read commands (refer to figure 32.) data delay after pd t compute 3.2 ms after t compute , all registers contain data from frst image after pd . note that an additional 75 frames for agc stabilization may be required if mouse movement occurred while pd was high. (refer to figure 11.) sdio write setup time t setup 60 ns data valid time before the rising of sclk (refer to figure 25.) pd pulse width t pdw 700 s pulse width to initiate the power down (to power down the chip) cycle @1500 fps (refer to figure 13.) pd pulse width t pd 100 s pulse width to reset the serial port (to reset the serial port) @1500 fps (but may also initiate a power down cycle) (refer to figure 11.) frame rate fr 1500 frames/s see frame_period register section bin resistor r1 15k 15k 37k refer to figure 8
figure 9. distance from lens reference plane to surface. ac electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25c, v dd = 3.3 v, 18 mhz, 1500 fps. parameter symbol min. typ. max. units notes power down t pd 700 s from pd time uncertainty due to frmware delay (refer to figure 11). power up from pd t pupd 50 ms from pd to valid quad signals 705 sec + 75 frames (refer to figure 11). power up from v dd t pu 30 ms from v dd to valid quad signals 705 sec + 40 frames rise and fall times sdio t r 15 ns c l = 30 pf (the rise time is between 10% to 90%) t f 12 ns c l = 30 pf (the fall time is between 10% to 90%) xa, xb, ya, yb t r 30 ns c l = 30 pf (the rise time is between 10% to 90%) t f 22 ns c l = 30 pf (the fall time is between 10% to 90%) iled t r 35 ns with hlmp-ed80-xx000 led (the rise time is between 10% to 90%). t f 170 ns with hlmp-ed80-xx000 led (the fall time is between 10% to 90%). serial port transaction timer t sptt 0.7 0.9 1.0 s serial port will reset if current transaction is not complete within t sptt (refer to figure 35). transient supply current i ddt 18 37 ma max supply current during a v dd ramp from 0 to 3.3v with > 500 ms rise time. does not include charging current for bypass capacitors. a d n s - 2 0 3 0 h d n s - 2 1 0 0 z o b j e c t s u r f a c e
dc electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25c, v dd = 3.3 v, 18 mhz. parameter symbol min. typ. max. units notes dc supply current (mouse moving) i dd avg 13 23 ma no load on xa, xb, ya, yb, sclk, sdio. excluding led current. peak supply current i dd peak 18 ma no load on xa, xb, ya, yb, sclk, sdio. (mouse moving) excluding led current. dc supply current i dd 10 23 ma no load on xa, xb, ya, yb, sclk, sdio. (mouse not moving) excluding led current. dc supply current (power down) i ddpd 4 30 a pd = v dd , sclk, sdio = gnd or v dd sclk, sdio, pd input low voltage v il 0.8 v input high voltage v ih 0.65 * v dd v output low voltage v ol 0.45 v @ i ol = 2 ma (sdio only) output high voltage v oh 0.6 * v dd v @ i oh = 2 ma (sdio only) output low voltage (xa, xb, ya, yb) v ol 0.6 v @i ol = 0.5 ma output high voltage (xa, xb, ya, yb) v oh 0.6 * v dd v @i oh = 0.5 ma output low voltage (xy_led) v ol 0.5 v refer to figure 10. xy led current i led typ C20% 614/r1 typ +20% a recommended operating conditions typ C15% 614/r1 typ +15% a @25c, v dd = 3.3 v (refer to figure 10 and table below). xy led current (fault mode) i led 1000 a r1 < 200 powerup xy led current i led 500 a v dd < 2.5 v figure 10. typical i-v characteristic of adns - 2030 xy_led pin. typical led current table r1 value k 15 18 22 27 33 37 led current (typical) ma 41 34 28 23 19 17 r1 = 15k r1 = 37k vol (v) normalized iled% 0 2.5 1.0 0.5 2.0 1.5 120 100 80 60 40 20 0
10 i d d t p d t p u p d p d 7 0 5 ? s 7 5 f r a m e s t c o m p u t e ( s e e f i g u r e 1 4 ) p d i l e d t c o m p u t e s c l k r e g i s t e r r e a d o p e r a t i o n ( p o w e r d o w n ) p d ~ 7 0 0 ? s t p d w l e d c u r r e n t o s c i l l a t o r s t a r t p d 2 5 0 ? s r e s e t c o u n t 4 5 5 ? s i n i t i a l i z a t i o n n e w a c q u i s i t i o n 2 4 1 0 ? s s c l k o p t i o n a l s p i t r a n s a c t i o n s w i t h o l d i m a g e d a t a 7 0 5 ? s t c o m p u t e s p i t r a n s a c t i o n s w i t h n e w i m a g e d a t a a t d e f a u l t f r a m e r a t e pd pin timing figure 11. pd timing C normal mode. figure 13. pd minimum pulse width. figure 12. pd timing C sleep mode. figure 14. detail of pd falling edge timing.
11 quadrature mode timing the output waveforms emulate the output from encod - ers. with the resolution set to 400 cpi, from one to fve quadrature states can exist within one frame time. the minimum state time is 133 s. if the resolution is 800 cpi, then up to ten quadrature states can exist within a frame time. if the motion within a frame is greater than these values, the extra motion will be reported in the next frame. the following diagrams (see figures 15, 16 and 17) show the timing for positive x motion, to the right, or positive y motion, up. if a power down via the pd pin occurs during a transfer, the transfer will resume after pd is de-asserted. the timing for that quadrature state will be increased by the length of the pd time. figure 15. quadrature states per frame (400 cpi mode). x a / y a x b / y b f i v e o r m o r e f o u r x a / y a x b / y b 2 6 7 ? s t h r e e x a / y a x b / y b 4 0 0 ? s t w o x a / y a x b / y b 5 3 3 ? s o n e x a / y a x b / y b 6 6 7 ? s ~ 6 6 7 ? s @ 1 5 0 0 f r a m e s / s e c o n d o n e f r a m e 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s 1 3 3 ? s x m o t i o n t o t h e r i g h t y m o t i o n u p
1 figure 16. quadrature states per frame (800 cpi mode). x a / y a x b / y b t e n o r m o r e n i n e x a / y a x b / y b e i g h t x a / y a x b / y b s e v e n x a / y a x b / y b s i x x a / y a x b / y b ~ 6 6 7 ? s @ 1 5 0 0 f r a m e s / s e c o n d o n e f r a m e 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 1 3 3 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 2 0 0 m s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 2 6 6 m s 3 3 3 ? s x m o t i o n t o t h e r i g h t y m o t i o n u p
1 figure 17. quadrature states per frame (800 cpi mode). x a / y a x b / y b f i v e f o u r x a / y a x b / y b t h r e e x a / y a x b / y b t w o x a / y a x b / y b o n e x a / y a x b / y b ~ 6 6 7 ? s @ 1 5 0 0 f r a m e s / s e c o n d o n e f r a m e 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 6 6 . 7 ? s 4 0 0 ? s 4 7 6 ? s x m o t i o n t o t h e r i g h t y m o t i o n u p
1 quadrature state machine the following state machine shows the states of the quadrature pins. the two things to note are that while the pd pin is asserted, the state machine is halted. once pd is de-asserted, the state machine picks up from where it left of. state 0 is entered after a power up reset. figure 18. quadrature state machine. quadrature output waveform the two channel quadrature outputs are 3.3 volt cmos outputs. the ? x count is used to generate the xa and xb signals, and ? y count is used for the ya and yb signals. figure 19. quadrature output waveform. s t a t e 0 s t a t e 2 s t a t e 3 s t a t e 1 + 1 - 1 - 1 + 1 + 1 - 1 - 1 + 1 p d p d p d p d s t a t e 0 1 2 3 x a n d y o u t p u t a 0 0 1 1 b 0 1 0 1 - 1 - 1 - 1 - 1 l e f t m o t i o n ( e d i r e c t i o n ) x a x b m o t i o n c o u n t + 1 + 1 + 1 + 1 r i g h t m o t i o n ( + d i r e c t i o n ) x a x b m o t i o n c o u n t + 1 + 1 + 1 + 1 u p m o t i o n ( + d i r e c t i o n ) y a y b m o t i o n c o u n t - 1 - 1 - 1 - 1 d o w n m o t i o n ( e d i r e c t i o n ) y a y b m o t i o n c o u n t
1 typical performance characteristics performance characteristics over recommended operating conditions. typical values at 25c, v dd = 3.3 v, 18 mhz. parameter symbol min. typ. max. units notes path error p error 0.5 % path error (deviation) is the error from the ideal cursor path. (deviation) it is expressed as a percentage of total travel and is measured over standard surfaces. the following graphs (figs 20C23) are the typical perfor - mance of the ADNS-2030 sensor, assembled as shown in the 2d assembly drawing with the hdns-2100 lens/prism, the hdns-2200 clip, and the hlmp-ed80-xx000 led (see figure 5). notes : 1. the adns- 0 0 is designed for optimal performance when used with the hlmp-ed 0-xx000 (red led nm). for use with other led colors (ie. blue, green), please consult factory. when using alternate leds there may also be performance degrada - tion and additional eye safety consideration. . z = distance from lens reference plane to surface. . dof = depth of field white paper manila folder burl formica dark walnut black copy recommended operating region dof height, z (mm) (2.4 = nominal focus) counts per inch 3.5 2.3 1.5 3.1 2.7 1.9 450 350 250 150 50 -50 figure 20. typical resolution vs. height, z. (comparative surfaces) dof z wavelength (nm) relative responsivity 400 100 0 700 500 900 800 600 1.0 0.8 0.6 0.4 0.2 0 figure 16. wavelength responsivity [1] . 100% 75% 50% recommended operating region do f height, z (mm) (2.4 = nominal focus) counts per inch 3.5 2.3 1.5 3.1 2.7 1.9 450 400 350 300 250 200 150 100 50 0 figure 22. typical resolution vs. height, z. (manila folder and led variation) [2,3] dof z 100% 75% 50% recommended operating region dof height, z (mm) (2.4 = nominal focus) counts per inch 3.5 2.3 1.5 3.1 2.7 1.9 450 400 350 300 250 200 150 100 50 0 -50 figure 23. typical resolution vs. height, z. (black copy and led variation) [2,3] dof z
1 s c l k s d i o s d i o d r i v e n b y m i c r o c o n t r o l l e r 1 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 s c l k c y c l e # d o n ' t c a r e s c l k s d i o t s e t u p = 6 0 n s , m i n 1 2 0 n s , m i n 1 2 0 n s 1 2 0 n s synchronous serial port the synchronous serial port is used to set and read pa - rameters in the ADNS-2030, and can be used to read out the motion information instead of the quadrature data pins. the port is a two wire, half duplex port. the host micro - controller always initiates communication; the adns- 2030 never initiates data transfers. sclk : the serial port clock. it is always generated by the master (the microcontroller). sdio : the data line. pd : a third line is sometimes involved. pd (power down) is usually used to place the adns - 2030 in a low power mode. pd can also be used to force re - synchronization between the microcontroller and the adns - 2030 in case of an error. figure 24 . write operation. figure 25. sdio setup and hold times sclk pulse width. write operation a write operation, which means that data is going from the microcontroller to the adns - 2030, is always initiated by the microcontroller and consists of two bytes. the frst byte contains the address (seven bits) and has a 1 as its msb to indicate data direction. the second byte contains the data. the transfer is synchronized by sclk . the mi - crocontroller changes sdio on falling edges of sclk . the ADNS-2030 reads sdio on rising edges of sclk.
1 s d i o d r i v e n b y m i c r o c o n t r o l l e r s d i o d r i v e n b y a d n s - 2 0 3 0 1 2 3 4 5 6 7 8 s c l k c y c l e # s c l k s d i o 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 d e t a i l " a " d e t a i l " b " 1 2 0 n s , m a x m i c r o c o n t r o l l e r t o a d n s - 2 0 3 0 s d i o h a n d o f f d e t a i l " a " a 0 1 2 0 n s , m i n s c l k s d i o h i - z 0 n s , m i n a 1 1 2 0 n s , m a x d 7 0 n s , m i n d 6 6 0 n s , m i n t h o l d 1 0 0 ? s , m i n a d n s - 2 0 3 0 t o m i c r o c o n t r o l l e r s d i o h a n d o f f d e t a i l " b " s c l k s d i o 1 2 0 n s , m i n d 0 1 0 n s , m a x r / w b i t o f n e x t a d d r e s s r e l e a s e d b y 2 0 3 0 d r i v e n b y m i c r o read operation a read operation, which means that data is going from the adns - 2030 to the microcontroller, is always initiated by the micro-controller and consists of two bytes. the frst byte contains the address, is written by the micro-controller, and has a 0 as its msb to indicate data direction. the second byte contains the data and is driven by the ADNS-2030. the transfer is synchronized by sclk . sdio is changed on falling edges of sclk and read on every rising edge of sclk . figure 26. read operation. figure 27. microcontroller to ADNS-2030 sdio handof. note: the 120 ns high state of sclk is the minimum data hold time of the ADNS-2030. since the falling edge of sclk is actually the start of the next read or write com - mand, the ADNS-2030 will hold the state of d 0 on the sdio line until the falling edge of sclk. in both write and read operations, sclk is driven by the microcontroller. the micro-controller must go to a high z state after the last address data bit. the ADNS-2030 will go to the high z state after the last data bit. (see detail b in figure 29). one other thing to note during a read operation is that sclk will need to be delayed after the last address data bit to ensure that the ADNS-2030 has at least 100 s to prepare the requested data. this is shown in the timing diagrams below. figure 28. ADNS-2030 to microcontroller sdio handof. serial port communications is not allowed while pd (power down) is high. see error detection and recovery regarding re-synchronizing via pd.
1 s c l k a d d r e s s d a t a t s w w ? 1 0 0 ? s w r i t e o p e r a t i o n a d d r e s s d a t a w r i t e o p e r a t i o n s c l k a d d r e s s d a t a w r i t e o p e r a t i o n a d d r e s s n e x t r e a d o p e r a t i o n t s w r ? 1 0 0 ? s d a t a t h o l d ? 1 0 0 ? s a d d r e s s t s r w a n d t s r r > 1 2 0 n s n e x t r e a d o r w r i t e o p e r a t i o n a d d r e s s s c l k r e a d o p e r a t i o n forcing the sdio line to the hi-z state there are times when the sdio line from the ADNS-2030 should be in the hi-z state. if the microprocessor has com - pleted a write to the ADNS-2030, the sdio line is hi-z, since the sdio pin is still confgured as an input. however, if the last operation from the microprocessor was a read, the ADNS-2030 will hold the d0 state on sdio until a falling edge of sclk. to place the sdio pin into the hi-z state, frst raise the pd pin for 100 s (min). the pd pin can stay high, with the ADNS-2030 in the shutdown state, or the pd pin can be lowered, returning the ADNS-2030 to normal opera - tion. in either case, the sdio line will now be in the hi-z state. figure 30. timing between two write commands. figure 31. timing between write and read commands. figure 32. timing between read and either write or subsequent read commands. s d i o p d h i - z 1 0 0 ? s figure 29. sdio hi-z state and timing. required timing between read and write commands there are minimum timing requirements between read and write commands on the serial port. see figure 30. if the rising edge of sclk for the last data bit of the sec - ond write command occurs before the 100 microsecond required delay, then the frst write command may not complete correctly. see figure 31. if the rising edge of sclk for the last address bit of the read command occurs before the 100 microsecond re - quired delay, then the write command may not complete correctly. see figure 32.
1 5. in case of synchronization failure, both the ADNS-2030 and the microcontroller may drive sdio. the adns- 2030 can withstand 30 ma of short circuit current and will withstand infnite duration short circuit condi - tions. 6. termination of a transmission by the microcontroller may sometimes be required (for example, due to a usb suspend interrupt during a read operation). to ac - complish this the microcontroller should raise pd. the adns - 2030 will not write to any register and will reset the serial port (but nothing else) and be prepared for the beginning of future transmissions after pd goes low. 7. the microcontroller can verify success of write opera - tions by issuing a read command to the same address and comparing written data to read data. 8. the microcontroller can verify the synchronization of the serial port by periodically reading the product id register. d a t a s c l k p d > 1 ? s error detection and recovery 1. the ADNS-2030 and the microcontroller might get out of synchronization due to esd events, power supply droops or microcontroller frmware faws. in such a case the microcontroller should raise pd for 100 s. the ADNS-2030 will reset the serial port but will not reset the registers, and be prepared for the beginning of a new transmission. 2. the ADNS-2030 has a transaction timer for the serial port. if the 16 th sclk rising edge is spaced more than approximately 0.9 seconds from the frst sclk edge of the current transaction, the serial port will reset. 3. invalid addresses: writing to an invalid address will have no efect. read - ing from an invalid address will return all zeros. 4. collision detection on sdio: the only time that the adns - 2030 drives the sdio line is during a read operation. to avoid data collisions, the microcontroller should relinquish sdio before the falling edge of sclk after the last address bit. the adns - 2030 begins to drive sdio after the next rising edge of sclk. the ADNS-2030 relinquishes sdio within 120 ns of the falling sclk edge after the last data bit. the microcontroller can begin driving sdio any time after that. in order to maintain low power consumption in normal operation or when the pd pin is pulled high, the micro-controller should not leave sdio foating un - til the next transmission (although that will not cause any communication difculties). the falling edge of sclk for the frst address bit of either the read or write command must be at least 120 ns after the last sclk rising edge of the last data bit of the previ - ous read operation. figure 33. timing between sclk and pd rising edge.
0 figure 34. power up serial port sequence. d a t a ? 0 x 0 3 a d d r e s s ? 0 x 0 0 s c l k s d i o p d v d d p r o b l e m a r e a notes on power up and the serial port the sequence in which v dd , pd, sclk and sdio are set during powerup can afect the operation of the serial port. the diagram below shows what can happen shortly after powerup when the microprocessor tries to read data from the serial port. this diagram shows the v dd rising to valid levels, at some point the microcontroller starts its program, sets the sclk and sdio lines to be outputs, and sets them high. it then waits to ensure that the ADNS-2030 has powered up and is ready to communicate. the microprocessor then tries to read from location 0x00, product_id, and is expecting a value of 0x03. if it receives this value, it then knows that the communication to the ADNS-2030 is operational. the problem occurs if the adns - 2030 powers up before the microprocessor sets the sclk and sdio lines to be outputs and high. the ADNS-2030 sees the raising of the sclk as a valid rising edge, and clocks in the state of the sdio as the frst bit of the address (sets either a read or a write depending upon the state). in the case of sdio low, then a read operation has started. when the microprocessor begins to actually send the address, the ADNS-2030 already has the frst bit of an address. when the 7 th bit is sent by the micro, the adns - 2030 has a valid address, and drives the sdio line high within 120 ns (see detail a in figure 26 and figure 27). this results in a bus fght for sdio. since the address is wrong, the data sent back will be incorrect. in the case of sdio high, a write operation is started. the address and data are out of synchronization, and the wrong data will be written to the wrong address.
1 two solutions there are two diferent ways to solve the problem: (1) waiting for the serial port watchdog timer to time out, or (2) using the pd line to reset the serial port. 1. serial port watchdog timer timeout (refer to figure 35.) if the microprocessor waits at least t sptt from v dd valid, it will ensure that the ADNS-2030 has powered up and the watchdog timer has timed out. this assumes that the mi - croprocessor and the ADNS-2030 share the same power supply. if not, then the microprocessor must wait t sptt from ADNS-2030 v dd valid. then when the sclk toggles for the address, the ADNS-2030 will be in sync with the microprocessor. 2. pd sync (refer to figure 36.) the pd line can be used to resync the serial port. if the microprocessor waits for 4 ms from v dd valid, and then outputs a valid pd pulse (refer to figure 14), then the serial port will be ready for data. resync note if the microprocessor and the ADNS-2030 get out of sync, then the data either written or read from the registers will be incorrect. an easy way to solve this is to output a pd pulse to resync the parts after an incorrect read. figure 35. power up serial port watchdog timer sequence. figure 36. power up serial port pd sync sequence. d a t a = 0 x 0 3 a d d r e s s = 0 x 0 0 s c l k s d i o p d v d d > t s p t t d a t a = 0 x 0 3 a d d r e s s = 0 x 0 0 s c l k s d i o p d v d d 4 m s
registers the ADNS-2030 can be programmed through registers, via the serial port, and confguration and motion data can be read from these registers. address register 0x00 product_id 0x01 revision_id 0x02 motion 0x03 delta_x 0x04 delta_y 0x05 squal address register 0x0c data_out_lower 0x0d data_out_upper 0x0e shutter_lower 0x0f shutter_upper 0x10 frame_period_lower 0x11 frame_period_upper product_id address: 0x00 access: read reset value: 0x03 bit 7 6 5 4 3 2 1 0 field pid 7 pid 6 pid 5 pid 4 pid 3 pid 2 pid 1 pid 0 data type : eight bit number with the product identifer. usage: the value in this register does not change; it can be used to verify that the serial communications link is ok. revision_id address: 0x01 access: read reset value: 0xnn bit 7 6 5 4 3 2 1 0 field pid 7 pid 6 pid 5 pid 4 pid 3 pid 2 pid 1 pid 0 data type: eight bit number with current revision of the ic. usage : nn is a value between 00 and ff which represent the current design revision of the device. ic revision nn rev. 1.0 0x10 rev. 2.0 0 x 20 address register 0x06 average_pixel 0x07 maximum_pixel 0x08 reserved 0x09 reseved 0x0a confguration_bits 0x0b reserved
motion address: 0x02 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field mot reserved fault ovfy ovfx reserved reserved res data type : bit feld usage: register 0x02 allows the user to determine if motion has occurred since the last time it was read. if so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. it also tells if the motion bufers have overfowed and whether or not an led fault oc - curred since the last reading. the current resolution is also shown. field name description mot motion since last report or pd 0 = no motion 1 = motion occurred, data ready for reading in delta_x and delta_y registers reserved reserved for future fault led fault detected C set when rbin is too low or too high, shorts to v dd or ground 0 = no fault 1 = fault detected ovfy motion overfow y, ? y bufer has overfowed since last report 0 = no overfow 1 = overfow has occurred ovfx motion overfow x, ? x bufer has overfowed since last report 0 = no overfow 1 = overfow has occurred reserved reserved reserved for future res resolution in counts per inch 0 = 400 1 = 800 notes for motion: 1. reading this register freezes the delta_x and delta_y register values. read this register before reading the delta_x and delta_y registers. if delta_x and delta_y are not read before the motion register is read a second time, the data in delta_x and delta_y will be lost. 2. avago recommends that registers 0x02, 0x03 and 0x04 be read sequentially. 3. internal bufers can accumulate more than eight bits of motion for x or y. if either one of the internal bufers overfows, then absolute path data is lost, and the ovfx or ovfy bit is set. to clear these bits (ovfx and ovfy), read the motion, delta_x and delta_y registers consecutive - ly. repeat until the motion bit (mot) is cleared. until mot is cleared, the delta_x or delta_y registers will read either positive or negative full scale, except possibly the last read. if the motion register has not been read for long time, at 400 cpi it may take up to 16 read cycles to clear the bufers, at 800 cpi, up to 32 cycles. 4. the fault bit signifes that an led fault has occurred since the last time the motion register was read. an led fault occurs if rbin has a low resistance connection to ground. when this is detected the led is turned of. the fault bit is set after a fault occurs. the fault bit remains set until the fault condition is cleared and the motion register is read. this bit is updated only when the motion register is read. once an led fault has cleared, the hardware will drive the led normally.
delta_x address: 0x03 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 data type: eight bit 2s complement number. usage: x movement is counts since last report. absolute value is determined by resolution. reading clears the register. 00 01 02 7e 7f +127 +126 +1 +2 ff fe 81 80 0 -1 -2 -127 -128 motion delta_x 00 01 02 7e 7f +127 +126 +1 +2 ff fe 81 80 0 -1 -2 -127 -128 motion delta_y delta_y address: 0x04 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 data type: eight bit 2s complement number. usage: y movement is counts since last report. absolute value is determined by resolution. reading clears the register
squal address: 0x05 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field sq 7 sq 6 sq 5 sq 4 sq 3 sq 2 sq 1 sq 0 data type: eight bit number. usage: squal (surface quality) is a measure of the number of features visible by the sensor in the current frame. the maximum value is 255. since small changes in the current frame can result in changes in squal, variations in squal when looking at a surface are expected. the graph below shows 250 sequentially acquired squal values, while a sensor was moved slowly over white paper. squal is nearly equal to zero, if there is no surface below the sensor. the focus point is important and could afect the squal value. figure 37 shows another setup with various z- height. this graph clearly shows that the squal count is dependent on focus distance. the data is obtained by getting multiple readings over diferent heights. 0 25 50 75 100 125 150 175 200 225 250 0 64 128 192 256 squal v alue squal v alues (white paper) delta from nominal focus (mm) normalized squal counts 1.0 0 -0.3 -1.0 -0.8 0.75 0.5 0.25 -0.5 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 figure 37. typical squal vs. height, z. (white paper) x + 3 x x ? 3
average_pixel address: 0x06 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field 0 0 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 data type: six bit number. usage: average pixel value in current frame. minimum value = 0, maximum = 63. the average pixel value may vary from frame to frame. shown below is a graph of 250 sequentially acquired average pixel values, while the sensor was moved slowly over white paper. maximum_pixel address: 0x07 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field 0 0 mp 5 mp 4 mp 3 mp 2 mp 1 mp 0 data type: six bit number. usage: maximum pixel value in current frame. minimum value = 0, maximum value = 63. the maximum pixel value may vary from frame to frame. shown below is a graph of 250 sequentially acquired maximum pixel values, while the sensor was moved slowly over white paper. 0 16 32 48 64 0 25 50 75 100 125 150 175 200 225 250 a verage pixel a verage pixel (white paper) 0 25 50 75 100 125 150 175 200 225 250 0 16 32 48 64 maximum pixel v alue maximum pixel (white paper)
reserved address: 0x08 reserved address: 0x09 confguration_bits address: 0x0a access: read/write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field reset led_mode self test res pixdump reserved reserved sleep data type : bit feld usage: register 0x0a allows the user to change the confguration of the sensor. shown below are the bits, their default values, and optional values. field name description reset power up defaults (bit always reads 0) 0 = no efect 1 = reset registers and bits to power up default settings (bold entries) led_mode led shutter mode 0 = shutter mode of (led always on, even if no motion up to 1 sec) 1 = shutter mode on (led only on when electronic shutter is open) self test [1] self tests (bit always reads 0) 0 = no tests 1 = perform all self tests, output 16 bit crc via data_out_upper and data_out_lower registers. res resolution in counts per inch 0 = 400 1 = 800 pix dump dump the pixel array through data_out_upper and data_out_lower, 256 bytes each 0 = disabled 1 = dump pixel array reserved reserved sleep sleep mode 0 = normal, falls asleep after one second of no movement (1,500 frames/s) 1 = always awake note: 1. since part of the self test is a ram test, the ram will be overwritten with the default values when the test is done. if any confguration changes from the default are needed for operation, make the changes after the self test is run. this operation requires substantially more time to complete than other register transactions.
reserved address: 0x0b data_out_lower address: 0x0c access: read reset value: undefned bit 7 6 5 4 3 2 1 0 field do 7 do 6 do 5 do 4 do 3 do 2 do 1 do 0 data_out_upper address: 0x0d access: read reset value: undefned bit 7 6 5 4 3 2 1 0 field do 15 do 14 do 13 do 12 do 11 do 10 do 9 do 8 data type: sixteen bit word. usage: data from the system self test or the pixel dump command can be read out with these registers. the data can be read from 0x0d only, or from 0x0d followed by 0x0c. data_out_upper data_out_lower notes self test result 1: db fd one of two results returned. self test result 2: 20 d6 these values are subject to change with each device design revision. pixel dump command: pixel address pixel data (bits 0-5) and pixel data status (bit 7) once the pixel dump command is given, the sensor writes the address and the value for the frst pixel into the data_out_upper and data_out_lower registers. the msb of data_out_lower is the status bit for the data. if the bit is high, the data are not valid. once the msb is low, the data for that particular read are valid and should be saved. the pixel address and data will then be incremented on the next frame. once the pixel dump is complete, the pixdump bit in register 0x0a should be set to zero. to obtain an accurate image to get the pixel dump image, the led needs to be turned on by changing the sleep mode of the confguration register 0x0a to always awake.
figure 38. directions are for a complete mouse, with the hdns-2100 lens. pixel address map (looking through the hdns-2100 lens) first pixe l last pixel 00 0f 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 10 1f 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 20 2f 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 30 3f 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 40 4f 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 50 5f 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 60 6f 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 70 7f 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 80 8f 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 90 9f 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e a0 af a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae b0 bf b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be c0 cf c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce d0 df d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de e0 ef e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ff f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe . rb lb t op x -ray v iew of mouse positive x positive y 9 a2030 yyww 1 8 16
0 pixel dump pictures the following images are the output of the pixel dump command. the data ranges from zero for complete black, to 63 for complete white. an internal agc circuit adjusts the shutter value to keep the brightest feature (max pixel) in the mid 50s. (a) white paper (b) manila folder (c) neoprene mouse pad (gray) (d) usaf test chart group 3, element 1, 8 line pairs per mm figure 39. pixel dump pictures.
1 the focus point is important and could afect the shutter value. figure 40 shows another setup with various z- heights. this graph clearly shows that the shutter value is dependent on focus distance. it shows average readings over diferent heights. figure 40. typical shutter vs. z (white paper). 0 2 5 5 0 7 5 100 125 150 175 200 225 250 0 16 32 48 64 shutter v alue (clock cycles) shutter v alues (white paper) shutter_lower address: 0x0e access: read reset value: 0x64 bit 7 6 5 4 3 2 1 0 field s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 shutter_upper address: 0x0f access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 data type: sixteen bit word. usage: units are clock cycles; default value is 64. read shutter_upper frst, then shutter_lower. they should be read consecutively. the shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. the shutter value may be diferent on every frame. for each frame, the shutter can only change by 1/16 of the current value. shown below is a graph of 250 sequentially acquired shutter values, while the sensor was moved slowly over white paper. 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 distance from nominal focus (mm) normalized shutter va lue (counts) 3 3 ? + x x x
the maximum value of the shutter is depen - dent upon the frame rate and clock frequen - cy. the formula for the maximum shutter value is: clock freq max shutter value = C 2816 frame rate frames/second max shutter shutter decimal hex upper lower 2300* 5010 0x1392 13 92 2000* 6184 0x1828 18 28 1500 9184 0x23e0 23 e0 1000 15184 0x3b50 3b 50 500 33184 0x81a0 81 a0 * note: to optimize tracking performance on dark surfaces, it is recommended that an adaptive frame rate based on shutter value be implemented for frame rates greater than 1500. <-- default max shutter clock freq the formula is: = = counts frame rate (2s complements hex) for an 18 mhz clock, below are the frame_period val - ues for popular frame rates. frame_period_lower address: 0x10 access: read/write reset value: 0x20 bit 7 6 5 4 3 2 1 0 field fp 7 fp 6 fp 5 fp 4 fp 3 fp 2 fp 1 fp 0 frame_period_upper address: 0x11 access: read/write reset value: 0xd1 bit 7 6 5 4 3 2 1 0 field fp 15 fp 14 fp 13 fp 12 fp 11 fp 10 fp 9 fp 8 data type: sixteen bit 2s complement word. usage: sets the frame rate. the frame period counter counts up until it overfows. units are clock cycles. for a clock frequency of 18 mhz, the following table shows the maximum shutter value. 1 clock cycle is 55.56 nsec.
ic register state after reset (power up or setting bit 7, register 0x0a) address register default value meaning 0x00 product_id 0x03 product id = 3 (fixed value) 0x01 revision_id 0xnn revision of ic (fixed value) (for each device design revision) 0x02 motion 0x00 no motion led = no fault no x data overfow no y data overfow resolution is 400 counts per inch 0x03 delta_x 0x00 no x motion 0x04 delta_y 0x00 no y motion 0x05 squal 0x00 no image yet to measure 0x06 average_pixel 0x00 no image yet to measure 0x07 maximum_pixel 0x00 no image yet to measure 0x08 reserved 0x09 reserved 0x0a confguration_bits 0x00 part is not reset led shutter mode is of no self tests resolution = 400 counts per inch pixel dump is disabled sleep mode is enabled 0x0b reserved 0x0c data_out_lower undefned no data to read 0x0d data_out_upper undefned no data to read 0x0e shutter_lower 0x64 initial shutter value 0x0f shutter_upper 0x00 initial shutter value 0x10 frame_period_lower 0x20 initial frame period value (corresponds to 1500 fps) 0x11 frame_period_upper 0xd1 initial frame period value (corresponds to 1500 fps) changing the frame rate results in changes in the maxi - mum speed, acceleration limits, and dark surface perfor - mance. frames/second counts frame_period decimal hex 2s comp upper lower 2300* 7826 0x1e92 0xe16e e1 6e 2000* 9000 0x2328 0xdcd8 dc d8 1500 12000 0x2ee0 0xd120 d1 20 1000 18000 0x4650 0xb9b0 b9 b0 500 36000 0x8ca0 0x7360 73 60 <-- default frame period <-- minimum frame period *note: to optimize tracking performance on dark surfaces, it is recommended that an adaptive frame rate based on shutter value be implemented for frame rates greater than 1500.
optical mouse design references application note an1179 eye safety calculation an1228 ordering information specify part number as follows: ADNS-2030 = sensor ic in a 16-pin staggered dip, 20 per tube. hdns-2100 = round optical mouse lens hdns-2100#001 = trimmed optical mouse lens hdns-2200 = led assembly clip (black) hdns-2200#001 = led assembly clip (clear) hlmp-ed80-xx000 = led for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 00-00 avago technologies, limited. all rights reserved. obsoletes -1en av0 -101 en - april , 00

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